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TiWi-R2 TRANSCEIVER MODULE
DATASHEET
SLOW (32 KHZ) CLOCK SOURCE REQUIREMENTS
The slow clock is always supplied from an external source. It is input on the SLOW_CLK pin, and can be a digital
signal in the range of VIO only. For slow clock frequency and accuracy refer to Table 14. The external slow clock
must be stable before the system exits from shut down mode.
Parameter [1]
Condition
Symbol
Min
Typ
Max
Unit
Input slow clock frequency
32768
Hz
Input slow clock accuracy
Input transition time T r /T f – 10% to 90%
WLAN, BT
T r /T f
+/-250
100
ppm
ns
Frequency input duty cycle
30
50
70
%
Input voltage limits
Square wave,
DC coupled
VIH
0.65 x VDDS
VDDS
V peak
VIL
0
0.35 x VDDS
Input impedance
Input capacitance
Rise and fall time
1
5
100
MW
pF
ns
Phase noise
1 kHz
-125
dBc/Hz
[1] Slow clock is a fail safe input
Table 14 Slow Clock Source Requirements
The information in this document is subject to change without notice.
330-0045-R4.0
Copyright ? 2010-2012 LS Research, LLC
Page 21 of 41
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